FRDY=0, BCLR=0, BVAL=0
CFIFO Port Control Register
| DTLN | Receive Data Length Indicates the length of the receive data. |
| Reserved | These bits are read as 0000. The write value should be 0000. |
| FRDY | FIFO Port Ready 0 (0): FIFO port access is disabled. 1 (1): FIFO port access is enabled. |
| BCLR | CPU Buffer Clear Note: Only 0 can be read. 0 (0): Does not operate 1 (1): FIFO buffer cleared on the CPU side. |
| BVAL | Buffer Memory Valid Flag 0 (0): Invalid 1 (1): Writing ended |